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| 6502_computer [2024/06/11 13:41] – austin | 6502_computer [2024/09/22 22:08] (current) – external edit 127.0.0.1 |
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| ===== Video Card ===== | ===== Video Card ===== |
| Currently using an ESP32 as a video card using FabGL. I discovered after going down this path that IRQ's can't be processed faster then 200khz. This does hinder performance as there are delays in the echo code. I will probably replace with a RPI Zero in the near future. | Currently using an ESP32 as a video card using FabGL. I discovered after going down this path that IRQ's can't be processed faster then 200khz. This does hinder performance as there are delays in the echo code. I will probably replace with a RPI Pico in the near future. |
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| It is wired through a 6522 VIA. I couldn't get the Control Lines to work with the ESP so the 8 data lines are OR'ed to trigger the IRQ on the ESP. | It is wired through a 6522 VIA. I couldn't get the Control Lines to work with the ESP so the 8 data lines are OR'ed to trigger the IRQ on the ESP. |
| Source Code: https://github.com/adrenlinerush/esp32teletype | Source Code: https://github.com/adrenlinerush/esp32teletype |
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| ====== RAM ====== | ===== RAM ===== |
| I have 28k available for use rather than the 16k in Ben's Design. To accomplish this I added a single MC14082B dual 4-input AND gate. Instead of tying A14 to the NAND gate with the Inverted A15 signal I AND A14,A13,A12,and A11 and then that goes into the NAND Gate and output to the CS of the 6522. A10 goes to the first VIA giving address of 7C00 and A9 to the second VIA with address of 7A. I also tie the output of the AND to the OE of RAM. With this I am able to use addresses 0000-6FFF for RAM and have the ability to add 5 more I/O devices. I would have thought I would be able to address 8 more pages but I am not. The RAM chip could be bad but I haven't bought another to try. | I have 28k available for use rather than the 16k in Ben's Design. To accomplish this I added a single MC14082B dual 4-input AND gate. Instead of tying A14 to the NAND gate with the Inverted A15 signal I AND A14,A13,A12,and A11 and then that goes into the NAND Gate and output to the CS of the 6522. A10 goes to the first VIA giving address of 7C00 and A9 to the second VIA with address of 7A. I also tie the output of the AND to the OE of RAM. With this I am able to use addresses 0000-6FFF for RAM and have the ability to add 5 more I/O devices. |
| ===== SD Card Storage ====== | ===== SD Card Storage ====== |
| I Added a second VIA addressed at 7A00 and have a microsd card SPI adapter plugged in there. I modified gfoot's source to compile with ca65 and work with my BIOS\Monitor and MSBASIC. I am able to list files with my monitor in root and nested directories. I am able to load them into memory, display as ASCII or HEX, or execute. | I Added a second VIA addressed at 7A00 and have a microsd card SPI adapter plugged in there. I modified gfoot's source to compile with ca65 and work with my BIOS\Monitor and MSBASIC. I am able to list files with my monitor in root and nested directories. I am able to load them into memory, display as ASCII or HEX, or execute. |
